The influence of parasitic capacitors on SAR ADC characteristics
نویسندگان
چکیده
Abstract: The analysis of the effect of the parasitic capacitors of the split capacitor array on the successive approximation register analog-to-digital converter’s charachteristics is presented. The Verilog-A model of the split capacitor array is developed based on the analysis. The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can be extracted from the circuit topology by using Calibre by Mentor Graphics or a similar tool. The influence of the two main parasitic capacitor types (those parallel to and those common to the capacitors in the arrays) on the DAC characteristics is analyzed. We provide expressions for fast manual calculation of the integral non-linearity (INL) and differential non-linearity (DNL) errors according to the values of the parasitic capacitors. Simulation results from a Verilog-A module based on this model are given.
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